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1 april 7, 2005 U630H64 s high-performance cmos nonvola- tile static ram 8192 x 8 bits s 25, 35 and 45 ns access times s 12, 20 and 25 ns output enable access times s hardware store initiation (store cycle time < 10 ms) s automatic store timing s 10 5 store cycles to eeprom s 10 years data retention in eeprom s automatic recall on power up s hardware recall initiation (recall cycle time < 20 s) s unlimited recall cycles from eeprom s unlimited read and write to sram s single 5 v 10 % operation s operating temperature ranges: 0 to 70 c -40 to 85 c s qs 9000 quality standard s esd characterization according mil std 883c m3015.7-hbm (classification see ic code numbers) s rohs compliance and pb- free s packages: pdip28 (300 mil) sop28 (330 mil) the U630H64 has two separate modes of operation: sram mode and nonvolatile mode, determined by the state of the ne pin. in sram mode, the memory ope- rates as an ordinary static ram. in nonvolatile operation, data is transferred in parallel from sram to eeprom or from eeprom to sram. in this mode sram functions are disabled. the U630H64 is a fast static ram (25, 35, 45 ns), with a nonvolatile electrically erasable prom (eeprom) element incorporated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resi- des in eeprom. data transfers from the sram to the eeprom (the store operation), or from the eeprom to the sram (the recall operation) are initiated through the state of the ne pin. the U630H64 combines the high performance and ease of use of a fast sram with nonvolatile data integrity. once a store cycle is initiated, further input or output are disabled until the cycle is completed. internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvola- tile information is transferred into the sram cells. the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. pin configuration pin description hardstore 8k x 8 nvsram top view 1 ne vcc 28 2 a12 w 27 4 a6 a8 25 5 a5 a9 24 3 a7 n.c. 26 6 a4 a11 23 7 a3 g 22 8 a2 a10 21 12 dq1 dq5 17 9 a1 e 20 10 a0 dq7 19 11 dq0 dq6 18 13 dq2 dq4 16 14 vss dq3 15 pdip sop signal name signal description a0 - a12 address inputs dq0 - dq7 data in/out e chip enable g output enable w write enable ne nonvolatile enable vcc power supply voltage vss ground features description
2 april 7, 2005 U630H64 block diagram truth table for sram operations operating mode e ne w g dq0 - dq7 standby/not selected h *** high-z internal read l h h h high-z read l h h l data outputs low-z write l h l * data inputs high-z * h or l characteristics all voltages are referenced to v ss = 0 v (ground). all characteristics are valid in the power supply voltage range and in the operating temperature range specified. dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of v i , as well as input levels of v il = 0 v and v ih = 3 v. the timing reference level of all input and output signals is 1.5 v, with the exception of the t dis -times and t en -times, in which cases transition is measured 200 mv from steady-state voltage. a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only, and functional operation of the device at condition above those indicated in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings a symbol min. max. unit power supply voltage v cc -0.5 7 v input voltage v i -0.3 v cc +0.5 v output voltage v o -0.3 v cc +0.5 v power dissipation p d 1w operating temperature c-type k-type t a 0 -40 70 85 c c storage temperature t stg -65 150 c eeprom array 128 x (64 x 8) store recall sram array 128 rows x 64 x 8 columns a5 a6 a7 a8 a9 a11 a12 store/ recall control row decoder v cc v ss v cc g ne e w dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 column i/o column decoder a0 a1 a2 a3 a4 a10 input buffers
3 april 7, 2005 U630H64 dc characteristics symbol conditions c-type k-type unit min. max. min. max. operating supply current b i cc1 v cc v il v ih t c t c t c = 5.5 v = 0.8 v = 2.2 v = 25 ns = 35 ns = 45 ns 90 80 75 95 85 80 ma ma ma average supply current during store c i cc2 v cc e w v il v ih = 5.5 v v cc -0.2 v v cc -0.2 v 0.2 v v cc -0.2 v 67ma standby supply current d (cycling ttl input levels) i cc(sb)1 v cc e t c t c t c = 5.5 v v ih = 25 ns = 35 ns = 45 ns 30 23 20 34 27 23 ma ma ma average supply current at t cr = 200 ns b (cycling cmos input levels) i cc3 v cc w v il v ih = 5.5 v v cc -0.2 v 0.2 v v cc -0.2 v 15 15 ma standby supply current d (stable cmos input levels) i cc(sb) v cc e v il v ih = 5.5 v v cc -0.2 v 0.2 v v cc -0.2 v 11ma recommended operating conditions symbol conditions min. max. unit power supply voltage v cc 4.5 5.5 v input low voltage v il -2 v at pulse width 10 ns permitted -0.3 0.8 v input high voltage v ih 2.2 v cc +0.3 v b: i cc1 and i cc3 are dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. the current i cc1 is measured for write/read - ratio of 1/2. c: i cc2 is the average current required for the duration of the store cycle (store cycle time). d: bringing e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. see mode selection table. the current i cc(sb)1 is measured for write/read - ratio of 1/2.
4 april 7, 2005 U630H64 dc characteristics symbol conditions c-type k-type unit min. max. min. max. output high voltage output low voltage v oh v ol v cc i oh i ol = 4.5 v =-4 ma = 8 ma 2.4 0.4 2.4 0.4 v v output high current output low current i oh i ol v cc v oh v ol = 4.5 v = 2.4 v = 0.4 v 8 -4 8 -4 ma ma input leakage current high low i ih i il v cc v ih v il = 5.5 v = 5.5 v = 0 v -1 1 -1 1 a a output leakage current high at three-state- output low at three-state- output i ohz i olz v cc v oh v ol = 5.5 v = 5.5 v = 0 v -1 1 -1 1 a a sram memory operations no. switching characteristics read cycle symbol 25 35 45 unit alt. iec min. max. min. max. min. max. 1 read cycle time f t avav t cr 25 35 45 ns 2 address access time to data valid g t avqv t a(a) 25 35 45 ns 3 chip enable access time to data valid t elqv t a(e) 25 35 45 ns 4 output enable access time to data valid t glqv t a(g) 12 20 25 ns 5e high to output in high-z h t ehqz t dis(e) 13 17 20 ns 6g high to output in high-z h t ghqz t dis(g) 13 17 20 ns 7e low to output in low-z t elqx t en(e) 555 ns 8g low to output in low-z t glqx t en(g) 000 ns 9 output hold time after addr. change g t axqx t v(a) 333 ns 10 chip enable to power active e t elicch t pu 000 ns 11 chip disable to power standby d, e t ehiccl t pd 25 35 45 ns e: parameter guaranteed but not tested. f: device is continuously selected with e and g both low. g: address valid prior to or coincident with e transition low. h: measured 200 mv from steady state output voltage.
5 april 7, 2005 U630H64 high impedance read cycle 1: ai-controlled (during read cycle: e = g = v il , w = ne = v ih ) f t a(a) previous data valid output data valid t cr address valid t v(a) ai dqi read cycle 2: g -, e -controlled (during read cycle: w = ne = v ih ) g ai e g t dis(e) t cr t a(e) t en(e) t en(g) t a(g) t dis(g) address valid output data valid i cc active standby t pd t pu no. switching characteristics write cycle symbol 25 35 45 unit alt. #1 alt. #2 iec min. max. min. max. min. max. 12 write cycle time t avav t avav t cw 25 35 45 ns 13 write pulse width t wlwh t w(w) 20 30 35 ns 14 write pulse width setup time t wleh t su(w) 20 30 35 ns 15 address setup time t av w l t avel t su(a) 000 ns 16 address valid to end of write t avwh t aveh t su(a-wh) 20 30 35 ns 17 chip enable setup time t elwh t su(e) 20 30 35 ns 18 chip enable to end of write t eleh t w(e) 20 30 35 ns 19 data setup time to end of write t dvwh t dveh t su(d) 12 18 20 ns 20 data hold time after end of write t whdx t ehdx t h(d) 000 ns 21 address hold after end of write t whax t ehax t h(a) 000 ns 22 w low to output in high-z h, i t wlqz t dis(w) 10 13 15 ns 23 w high to output in low-z t whqx t en(w) 555 ns (1) (2) (9) (1) (3) (4) (5) (7) (6) (8) 10 (11) t a(a) (2) dqi output output
6 april 7, 2005 U630H64 l- to h-level undefined h- to l-level i: if w is low and when e goes low, the outputs remain in the high impedance state. j: e or w and ne must be > v ih during address transitions. write cycle #1: w -controlled j write cycle #2: e -controlled j t h(d) t cw t su(e) t h(a) t w(w) t su(d) t dis(w) t en(w) address valid input data valid high impedance t su(a-wh) (12) (16) (13) (19) (20) (23) (21) t su(a) t h(d) t cw t w(e) t h(a) t su(d) address valid input data valid t su(w) (12) (18) (21) (20) (19) (17) (22) previous data valid (15) (14) high impedance (15) t su(a) ai e w dqi input dqi output ai e w dqi input dqi output
7 april 7, 2005 U630H64 nonvolatile memory operations no. store cycle inhibit and automatic power up recall symbol min. max. unit alt. iec 24 power up recall duration k, e t restore 650 s low voltage trigger level v switch 4.0 4.5 v k: t restore starts from the time v cc rises above v switch . store cycle inhibit and automatic power up recall v cc 5.0 v store inhibit power up v switch t restore recall (24) t mode selection e w g ne mode power notes l h l l nonvolatile recall active l l l h l nonvolatile store i cc2 l l l h l h l * no operation active * h or l l: an automatic recall also takes place at power up, starting when v cc exceeds v switch and takes t restore . v cc must not drop below v switch once it has been exceeded for the recall to function properly.
8 april 7, 2005 U630H64 t su(g)s t su(n)s t w(w)s t su(e)s t d(w)s t su(n)s t su(g)s t su(w)s t w(e)s t d(e)s high impedance high impedance (25) (29) (26) (28) (27) (30) (31) (33) (32) (34) ne g w e dqi output ne w e dqi output g store cycles no. store cycle w -controlled symbol min. max. unit alt. iec 25 store cycle time m t wlqx t d(w)s 10 ms 26 store initiation cycle time n t wlnh t w(w)s 25 ns 27 output disable setup to ne fall t ghnl t su(g)s 5ns 28 ne setup t nlwl t su(n)s 5ns 29 chip enable setup t elwl t su(e)s 5ns store cycle: w -controlled o no. store cycle e -controlled symbol min. max. unit alt. iec 30 store cycle time t elqxs t d(e)s 10 ms 31 store initiation cycle time t elnhs t w(e)s 25 ns 32 output disable setup to e fall t ghel t su(g)s 5ns 33 ne setup t nlel t su(n)s 5ns 34 write enable setup t wlel t su(w)s 5ns store cycle: e -controlled o
9 april 7, 2005 U630H64 t w(n)r t su(g)r t su(w)r t su(e)r t d(n)r t dis(n)r t su(n)r t su(g)r t su(w)r t w(e)r t d(e)r high impedance (36) (37) (38) (40) (35) (39) (41) (42) (43) (45) (44) high impedance ne g w e dqi output ne g w e dqi output recall cycles no. recall cycle ne -controlled symbol min. max. unit alt. iec 35 recall cycle time p t nlqx t d(n)r 20 s 36 recall initiation cycle time q t nlnh t w(n)r 25 ns 37 output enable setup t glnl t su(g)r 5ns 38 write enable setup t whnl t su(w)r 5ns 39 chip enable setup t elnl t su(e)r 5ns 40 ne fall to output inactive t nlqz t dis(n)r 25 ns recall cycle: ne -controlled o no. recall cycle e -controlled symbol min. max. unit alt. iec 41 recall cycle time t elqxr t d(e)r 20 s 42 recall initiation cycle time t elnhr t w(e)r 25 ns 43 ne setup t nlel t su(n)r 5ns 44 output enable setup t glel t su(g)r 5ns 45 write enable setup t whel t su(w)r 5ns recall cycle: e -controlled o
10 april 7, 2005 U630H64 t su(n)r t su(w)r t w(g)r t d(g)r high impedance (48) (47) (49) (50) (46) ne g w e dqi output t su(e)r no. recall cycle g -controlled symbol min. max. unit alt. iec 46 recall cycle time t glqxr t d(g)r 20 s 47 recall initiation cycle time t glnh t w(g)r 25 ns 48 ne setup t nlgl t su(n)r 5ns 49 write enable setup t whgl t su(w)r 5ns 50 chip enable setup t elgl t su(e)r 5ns recall cycle: g -controlled o, r m: measured with w and ne both returned high, and g returned low. note that store cycles are inhibited/aborted by v cc < v switch (store inhibit). n: once t w(w)s has been satisfied by ne , g , w and e , the store cycle is completed automatically. any of ne , g , w and e may be used to terminate the store initiation cycle. o: if e is low for any period of time in which w is high while g and ne are low, than a recall cycle may be initiated. for e -controlled store during t w(e)s w , g , ne have to be static. p: measured with w and ne both high, and g and e low. q: once t w(n)r has been satisfied by ne , g , w and e , the recall cycle is completed automatically. any of ne , g or e may be used to terminate the recall initiation cycle. r: if w is low at any point in which both e and ne are low and g is high, than a store cycle will be initiated instead of a recall.
11 april 7, 2005 U630H64 test configuration for functional check v ih v il v ss v cc t 480 255 30 pf s v o simultaneous measure- ment of all 8 output pins input level according to the relevant test measurement dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 e w g 5 v ne s: in measurement of t dis -times and t en -times the capacitance is 5 pf. t: between v cc and v ss must be connected a high frequency bypass capacitor 0.1 f to avoid disturbances. capacitance e conditions symbol min. max. unit input capacitance v cc v i f t a = 5.0 v = v ss = 1 mhz = 25 c c i 8pf output capacitance c o 7pf all pins not under test must be connected with ground by capacitors. operating temperature range c = 0 to 70 c k = -40 to 85 c 25 c s U630H64 type esd class blank > 2000 v b > 1000 v package d = pdip28 (300 mil) s = sop28 (330 mil) type 1 s2 = sop28 (330 mil) type 2 ordering code leadfree option blank = standard package g1 = leadfree green package u access time 25 = 25 ns 35 = 35 ns u 45 = 45 ns u device marking (example) u: on special request example g1 date of manufacture (the first 2 digits indicating the year, and the last 2 digits the calendar week.) leadfree green package product specification internal code zmd U630H64sc 25 z 0425 g1
12 april 7, 2005 U630H64 device operation the U630H64 has two separate modes of operation: sram mode and nonvolatile mode, determined by the state of the ne pin. in sram mode, the memory opera- tes as a standard fast static ram. in nonvolatile mode, data is transferred from sram to eeprom (the store operation) or from eeprom to sram (the recall operation). in this mode sram functions are disabled. sram read the U630H64 performs a read cycle whenever e and g are low while w and ne are high. the address specified on pins a0 - a12 determines which of the 8192 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t cr . if the read is initiated by e or g , the outputs will be valid at t a(e) or at t a(g) , whichever is later. the data outputs will repeatedly respond to address changes within the t cr access time without the need for transition on any control input pins, and will remain valid until another address change or until e or g is brought high or w or ne is brought low. sram write a write cycle is performed whenever e and w are low and ne is high. the address inputs must be sta- ble prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on pins dq0 - 7 will be written into the memory if it is valid t su(d) before the end of a w control- led write or t su(d) before the end of an e controlled write. it is recommended that g is kept high during the en- tire write cycle to avoid data bus contention on the common i/o lines. if g is left low, internal circuitry will turn off the output buffers t dis (w) after w goes low. noise consideration the U630H64 is a high speed memory and therefore must have a high frequency bypass capacitor of appro- ximately 0.1 f connected between v cc and v ss using leads and traces that are as short as possible. as with all high speed cmos ics, normal carefull routing of power, ground and signals will help prevent noise problems. hardware nonvolatile store a store cycle is performed when ne , e and w are low while g is high. while any sequence to achieve this state will initiate a store, only w initiation and e initiation are practical without risking an unintentional sram write that would disturb sram data. during a store cycle, previous nonvolat ile data is erased and the sram contents are then programmed into nonvola- tile elements. once a store cycle is initiated, further input and output is disabled and the dq0 - 7 pins are tristated until the cycle is completed. if e and g are low and w and ne are high at the end of the cycle, a read wi ll be performed and the out- puts will go active, indicating the end of the store. hardware nonvolatile recall a recall cycle is performed when e , g and ne are low while w is high. like the store cycle, recall is initiated when the last of the three clock-signals goes to the recall state. once initiated, the recall cycle will take ?recall cycle time? to complete, during which all inputs are ignored. when the recall com- pletes, any read or write state on the input pins will take effect. internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvolatile information is transferred into the sram cells. the recall in no way alters the data in the nonvolatile cells. the nonvolatile data can be recalled an unlimited number of times. like the store cycle, a transition must occur on some control pins to cause a recall, preventing inadver- tend multi-triggering. automatic power up recall on power up, once v cc exceeds the sense voltage of v switch , a recall cycle is automatically initiated. the voltage on the v cc pin must not drop below v switch once it has risen above it in order for the recall to operate properly. due to this automatic recall, sram operation cannot commence until t restore after v cc exceeds v switch . if the U630H64 is in a write state at the end of power up recall, the sram data will be corrupted. to help avoid this situation, a 10 k ? resistor should be connected between w and system v cc . hardware protection the U630H64 offers two levels of protection to sup- press inadvertent store cycles. if the control signals (e , g , w and ne ) remain in the store condition at the end of a store cycle, a second store cycle will not be started. the store (or recall) will be initiated only after a transition on any one of these signals to the required state. in addition to multi-trigger protection, the U630H64 offers hardware protection through v cc sense. when v cc < v switch the externally initiated store operation will be inhibited.
13 april 7, 2005 U630H64 the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. low average active power the U630H64 has been designed to draw significantly less power when e is low (chip enabled) but the access cycle time is longer than 55 ns. when e is high the chip consumes only standby cur- rent. the overall average current drawn by the part depends on the following items: 1. cmos or ttl input levels 2. the time during which the chip is disabled (e high) 3. the cycle time for accesses (e low) 4. the ratio of reads to writes 5. the operating temperature 6. the v cc level
zentrum mikroelektronik dresden ag grenzstra?e 28 ? d-01109 dresden ? p. o. b. 80 01 34 ? d-01101 dresden ? germany phone: +49 351 8822 306 ? fax: +49 351 8822 337 ? email: memory@zmd.de ? http://www.zmd.de U630H64 april 7, 2005 life support policy zmd products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the zmd product could create a situation where personal injury or death may occur. components used in life-support devices or systems must be expressly authorized by zmd for such purpose. limited warranty the information in this document has been carefully checked and is believed to be reliable. however zentrum mikroelektronik dresden ag (zmd) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. the information in this document describes the type of component and shall not be considered as assured charac- teristics. zmd does not guarantee that the use of any information contained herein will not infringe upon the patent, trade- mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. this document does not in any way extent zmd?s warranty on any product beyond that set forth in its standard terms and conditions of sale. zmd reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.

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